Regulated DC Power Supply Topologies

Simple DC electronic circuits can be powered by directly connecting a battery.

However, circuits usually require a constant input voltage for proper operation.

This log is a small parenthesis to explain the different regulated DC power supply topologies, before looking at the FunKey power supply schematics in details.

If you are already comfortable with this subject, you can skip this log entirely!

Linear Regulators

The easiest method to achieve this constant load voltage despite a varying source voltage is to linearly control the resistance of the regulator in accordance with the load, resulting in a constant output voltage.

Shunt Regulator

The simplest voltage regulator is the shunt regulator, built around a Zener diode which most interesting characteristic is to maintain a constant voltage across itself when the current through it is sufficient to take it into the Zener breakdown region. A simple shunt regulator looks like this:

Series Regulator

By adding a emitter-follower transistor to the simple shunt regulator, the small base current of the transistor forms a very light load on the Zener, thereby minimizing variation in Zener voltage due to variation in the load, resulting in a better regulation. Here is a schematic for this series regulator:

Integrated Linear Regulator

In integrated voltage regulators, the discrete Zener diode is replaced by a more sophisticated (but easier to integrate) circuit built around a resistor divider feeding an operational amplifier, a voltage reference, and a transistor driving the emitter-follower pass transistor:

Usually, the pass transistor and its driving transistor are combined into a single Darlington transistor plus a controllable current source like this:

LDO (Low Drop-Out) Regulator

The above circuit works well, but its drop-out voltage (the difference between the input and output voltage) is rather high because of this transistor cascade, around 1.5V to 2.5V.

By replacing the emitter-follower Darlington transistor by a PNP transistor in an open collector or open drain topology, the drop-out voltage is reduced to 0.7V or lower:

SMPS (Switched-Mode Power Supply) or DC/DC Converters

A linear regulator provides the desired output voltage by dissipating excess power as heat in the Zener diode or in the pass transistor. Hence its maximum power efficiency is VOUT/ VIN since the volt difference is wasted to heat the birds.

In contrast, a Switched-Mode Power Supply changes output voltage and current by switching non-linear storage elements, such as inductors, transformers and capacitors between different electrical configurations.

These elements are non-linear because the inductor and transformer respond to changes in current by inducing its own voltage to counter the change in current, whereas a capacitor responds to changes in voltage by inducing its own current to counter the change in voltage.

Thus, depending on the way the components are arranged, it is possible to obtain SMPS circuits that either have an output voltage higher than the input voltage (“Boost Converters”), or lower than the input voltage (“Buck Converters”, as is it subtracts or “Bucks” the supply voltage).

Because of technology, power inductors are easier to manufacture, take less space and are more stable over time than their counterpart capacitors. This is why most power DC/DC converters are built using inductors. Capacitor-based SMPS are generally used for lower power applications, such as for generating the +12V and -12V voltages required by true RS232 from a +3.3V or +5V power supply in the ubiquitous MAX232 drivers.

Boost Converter

The most basic circuit for the Boost converter is the following:

If the switch is driven by a square wave, the peak-to-peak voltage of the waveform measured across the switch can exceed the input voltage from the DC source. This is because the non-linear characteristic of the inductor, and this voltage adds to the source voltage while the switch is open.

Please note that in this converter, the output voltage is not isolated from the input voltage.

Buck Converter

The corresponding basic circuit for the Buck converter is the following:

The way this converter works is described in details here. Basically, when the switch is closed, the inductor will produce an opposing voltage across its terminals in response to the changing current, reducing the output voltage, and meanwhile the inductor stores this energy in the form of a magnetic field. When the switch is opened,  the current will decrease and will produce a voltage drop across the inductor, and now the inductor becomes a current source, where the stored energy in the inductor’s magnetic field is restored and fed to the load.

Please note that in this converter too, the output voltage is not isolated from the input voltage.

Isolated SMPS

Isolated Switched-Mode Power Supplies use a transformer to isolate the input voltage from the output voltage, and thus can produce an output of higher or lower voltage than the input by adjusting the turns ratio.

Advantages and Disadvantages

Linear regulators are simpler than SMPS, and their linear behavior produce a very clean output voltage, but their efficiency is directly proportional to the difference between the input and output voltage, which is dissipated as heat.

However, for light loads and/or when the voltage drop-out is low, LDOs are very useful.

OTOH, SMPS are more complex and require more components, but their efficiency is much better (typically 80-90%), resulting in less heat, with the drawback of a switching electrical noise pollution of both the input voltage (that may couple electrical switching noise back onto the mains power line) and the output voltage (with electromagnetic interference (EMI) and a ripple voltage at the switching frequency and all its harmonic frequencies).

SMPS are thus almost exclusively used when heavy loads are used and/or when the voltage drop-out is important.

Schematics: CPU

Schematics: CPU

At the heart of the FunKey electronic design is the CPU block, built around the Allwinner V3s chip:

We selected this particular chip because it features a built-in 64MB DDR2 DRAM, which is very good as it saves some precious real-estate on the PCB and also because its layout is much easier: usually because of the mandatory high-speed signals, DDR DRAM requires both length and impedance-matching on all critical signals, leading to the weird “snake”-style layout to balance traces. As here the DDR DRAM is bonded to the CPU into the same package, there is no such requirement here.

OTOH, 64 MB DRAM may not seem much, but we determined that it is sufficient for our modest retro-gaming needs.

One bonus with the V3s is that it comes into a non-BGA (Ball Grid Array) LQFP128 package with actual leads, which is much more user-friendly for prototyping!

Here is the part of the schematics corresponding to the CPU core:

SoC Blocks

As one can see, there is not much besides the CPU chip U3 itself… But it can also bee seen that the CPU is in fact a SoC (System on Chip) containing a collection of built-in peripheral and memory blocks along with the CPU itself:

  • the LCD / CSI display peripheral
  • the GPIO port G / SDC1 (SD Card #1) interface
  • the AUDIO codec
  • the LRADC0 (Low-Resolution Analog to Digital Converter)
  • the USB OTG controller
  • the GPIO port F / SDC0 (SD Card #0) / UART0 interface
  • the RTC (Real Time Clock) timer
  • the EPHY (Ethernet PHYsical) interface
  • the MIPI camera interface
  • the built-in 64 MB DDR2 DRAM
  • the GPIO port C / SPI interface
  • the GPIO port B / UART2 / PWM0 / PWM1 / TWI0 (I2C #0)  / TWI1 (I2C #1)

Among these, the FunKey device only uses a few blocks: the AUDIO, USB (as device only), SDC0 (for SD Card), RTC, DRAM, SPI (for the LCD screen), PWM0 (for backlight), TWI0 (for I2C bus to control the GPIO expander and power management chips) and a couple of GPIOs to power the audio power amplifier and get feedback interrupt signals from the the GPIO expander and power management chips.

CPU Power Supplies

What is remarkable though is that the V3s requires a lot of different voltages for its power supply:

  • +3V3 for the I/O power supply
  • +3V3_AO for the Always-On power supply (RTC timer)
  • +3V0 for analog power supply
  • +1V8 for the DDR2 DRAM power supply
  • +1V25 for the core power supply

This profusion of different power supplies as well as the high power drawn by some of them (1.2A for +3V3, 1.6A for +1.25V) requires a sophisticated power management that will be detailed in a future log.


The LRADC0 (Low-Resolution Analog to Digital Converter #0) is designed to measure the voltage of a resistor ladder switched by keyboard keys: this single input is thus in theory able to manage a keyboard of up to 10 keys @ 250 Hz.

Unfortunately, the FunKey has 12 keys (U/D/L/R, A/B/X/Y, RR/RL, START and SELECT), and the resulting key detection accuracy is not compatible with a gaming usage because of long term stability problems. This is the reason why it is not used in the FunKey and just terminated by a proper low-pass filter R6/C9 to avoid picking up noise glitches.

SD Card

The SD Card interface is almost a direct connection between the chip and the dedicated SD Card connector. Only a single series resistor R8 is required on the clock line in order to prevent ringing.


The V3s chips requires 2 crystals: one low-frequency 32.768 kHz crystal Y1 for the RTC clock and one high-frequency 24 MHz crystal Y2 for deriving the 1.2 GHz clock.

The 24 MHz crystal is used by an internal oscillator to lock the phase of the 1.2 GHz oscillator using a PLL (Phase-Locked Loop).

The 32.768 kHz crystal is used by another internal oscillator to tick the RTC (Real-Time Clock) at a standard watch frequency.

These crystals require 2 load capacitors (C12/C13 and C14/C15) each in order to guarantee that the oscillators still start and work with a comfortable operation margin taking into account voltage, temperature and aging.

The 32.768 kHz crystal features an additional high-value resistor R12 in order to limit the internal oscillator’s output current and thus reduce further the RTC timer power consumption.

For more details on crystal oscillator design, please check this application note from STM.


The DRAM within the V3s chip is a DDR2 one, meaning that its data lines are clocked using both edges of a 400 MHz clock signal.

At these high frequencies, even short wires have a length that is of the same order of magnitude as the signal’s wavelength and thus each signal should be considered as a transmission line, for which impedance must be matched to avoid signal reflections, requiring termination resistors on the data lines DQx.

DDR2 or DDR3 DRAMs feature merged drivers and dynamic on-chip termination like this (“VDDQ/2” is labeled “SVREF” in our schematic):

The V3s DDR2 DRAM has an active termination calibration circuitry and procedure called “ZQ Calibration” requiring an accurate 1% 240R resistor R11 (and NOT 240K like shown in the schematic, my mistake!) connected internally like this:

More on the DDR2 DRAM ZQ Calibration subject can be found in this Micron Application Note.

This concludes the study of the FunKey CPU core schematic block.

Electronic Parts

The main part in the FunKey device is of course the CPU: an AllWinner V3s SoC with integrated 64MB DDR2 DRAM. Not much compared to a Raspberry Pi for example, but it turns out it has just the right capacity for our purpose, and a minimum size because of its integrated DDR2 RAM, without the length and impedance-controlled constraints on PCB trace requirements.

The V3s also features a low power consumption and all the required peripheral that we need.

The V3s CPU is generally used with a companion AXP209 PMIC chip in charge of supplying all the required voltages for the CPU: +3V3, +3V3 (RTC), +3V0, +1V25, most of these using integrated DC/DC buck converters or simpler LDOs for the ones requiring the less power. The AXP209 also features an integrated Coulomb counter for monitoring the available battery power, as well as a soft-power switch controller that acts just like the one in your smartphone!

A separate AP3418KTR-G1 DC/DC converter is sued for providing the DDR2 DRAM +1V8 power.

The second most important part in our design is probably our small 1.5″ LCD screen. It has an amazing 240 x 240 pixel resolution, while using a simple SPI-based interface and not a complex DSi interface based on the differential high-speed MIPI specification, which requires a dedicated controller that is only available in higher-end SoC:

For audio playback, we wanted to have an internal speaker. But given the reduced dimensions, we tried to find the smallest available one, which has a very small 10 mm diameter, with a total height of 2.9 mm, out of which 1.4 mm can be inserted into a PCB hole, thus only having a height above PCB of 1.5 mm:

We use a simple mono audio playback through a PAM8301AAF amplifier. This amp has all the required characteristics, with a filterless (no capacitor) design.

After testing tactile domes in our FunKey Zero prototype, we decided to go back to standard tactile switches, as their placement can be done by a regular SMT pick&place machine with a very good accuracy, just like all the other components on the PCB, unlike the tactile domes which require an adhesive tape to place them, making them less accurate in their absolute positioning.

We also need some right-angled tactile switches for the rear left and right buttons:

We took the smallest we could get, but we may experiment with softer (no-click) ones for the rear buttons to bring a better play experience.

For the microUSB connector we choose a common mid-mount model with through-hole pins in order to avoid tearing it off the board if you don’t pull the chord straight. 

The only remaining mechanical part is the small DF37NB-24DS-0.4V(51) connector, matching the LCD screen connector.

For debug, we features a 3-pin  1.27 mm pitch header, with console UART RX, TX and GND pins.

The only remaining active part is a P-MOSFET used to drive the screen backlight from a V3s GPIO pin.

We use TVS diodes on all user-accessible parts to prevent ESD (these are small 0402 TVS), and a dedicated USB ESD protection a close as possible to the USB connector.

All other parts are passive resistors, capacitors or ferrite beads in 0402 form factor whenever possible, as we don’t have a lot of available real estate on this board.

As you can see, none of the components was chosen randomly, and finding the right part took us a significant amount of time!

Schematics: USB

In the FunKey device, the USB interface has 2 purposes:

  • provide an external power supply source for both powering the device and charging the built-in LiPo battery
  • provide a data interface to transfer firmware upgrades, configuration files, game emulators and game ROMs

The first purpose only requires the +5V USB power and GND pins. The second purpose requires to wire the additional differential data lines D+ and D-. As we only need to operate as an USB device and although the V3s is able to work as either an USB host or USB device using the USB OTG protocol, we don’t need the ID pin to determine by the cable wiring which role we must take.

The USB schematic is the following:

Before connecting 2 devices using an USB cable, they may be at completely different absolute voltages, and during cable insertion, the shield will be in contact before the other pins, including GND. The C6 capacitor between the Protective Earth (Shield) and GND is here to provide an AC path for sinking this difference in voltage and align the GND levels when plugin the cable. 

The resistor R4 on the USB ID connector pin should probably not be mounted: as we act only as an USB device, this pin should be left floating.

The capacitors C7, C8, C10 and ferrite bead L2 form a constant-k 3 pole CLC low pass filter to remove any spurious in/out on the USB power supply wire. The USB 2.0 specification limits the maximum bulk capacitance value to 10 µF in order to avoid power supply excessive droops when plugin in a device with a discharged large bulk capacitor.

D15 is a combined TVS protection diode for the VBUS pin and a set of clamping diodes that will limit the voltage on D+ and D- pins to stay between GND and VBUS levels to  in order to protect the V3s USB driver from under / over-voltages.

Schematics: Audio

Playing audio is absolutely part of the gaming experience!

So for a retro gaming console like the FunKey, we need to have a decent audio playback, despite its lilliputian size.

By decency, we discarded the solution using a piezo-electric buzzer: these can get a loud sound in a small volume, but only at their resonance frequency, so the sound quality is extremely poor.

Turning back to the solutions used in modern smartphones as an example, there are 2 paths to consider:

  • playing audio internally by the mean of speaker(s)
  • playing audio externally by using headphones, with or without a cord

The speakers used in today’s smartphones are rather sophisticated and achieve very good performance. However, these are using made-to-measure speakers and cavities, such that they cannot be found and reused as standard parts in a design like ours.

As for the external audio solution, we have a problem: the FunKey is so small that it is not possible to integrate an audio jack to connect headphones! And despite our search, there is no simple and small enough way to use Bluetooth to output audio to cordless headphones either.

The best solution we have found consists in using a single tiny speaker from CUI CDM-10008, that is able to output 72 dB spl @ 1m from a 0.3W input power, with relatively modest dimensions: 10 mm diameter and only a 2.9 mm thickness.

Connections are not easy though, since this speaker is meant to have wires soldered to its pads, but we are trying to convert it into an SMT device in order to gain space in our small enclosure! We don’t have a satisfying solution yet that is possible to use for mass production, we are still working on it!


The resulting schematic is simple, as the Allwinner V3s already contains an analog stereo audio codec (coder/decoder): we only have to take one of its headphone output channel (left or right) and feed it to a mono audio amplifier.

We chose the PAM8301 chip because of its cheap price, good availability, its more than sufficient output power of 1.5W and its filterless operation, meaning that no bulky series capacitor is required to drive the speaker.

Here is the corresponding schematic:

We chose the right headphone channel HPOUTR that is fed to the audio amplifier U2 through a DC-bias filter capacitor C3.

The audio amplifier /SD shutdown input is driven by one V3s GPIO, with a pull-down resistor R2 to disable the amplifier by default.

The audio amplifier power supply is filtered using a ferrite bead L1 in order to eliminate high-frequency digital noise, and decoupled by 2 capacitors C4 and C5, as recommended in the device datasheet.

The speaker SP1 is driven in differential mode in order to get the maximum voltage swing and thus the maximum power available for a given output current.

Two ESD protection TVS diodes D13 and D14 are added, since the speaker may be accessible to the user through the enclosure grid in front of the speaker.

Schematics: Buttons

As a generic game console emulating many classic ones, the FunKey requires numerous buttons:

  • A soft “ON/OFF” button
  • A “+” control pad with “Up”, “Down”, “Left” and “Right” buttons
  • A “x” control pad with “A”, “B”, “X” and “Y” buttons
  •  “Start” and a “Select” buttons
  • L and R shoulder buttons

As we have sen in the log on the PMIC, the soft “ON/OFF” button is directly connected to the power management chip, so we are left with 4 + 4 + 2 = 12 buttons for game control.

GPIO Requirements

The Allwinner v3s CPU comes in a large 128-pin TQFP package, with a lot of exposed (51!) GPIO pins:

  • PB0 to PB9 (10)
  • PC0 to PC3 (4)
  • PE0 to PE24 (25)
  • PF0 to PF5 (6)
  • PG0 to PG5 (6)

The FunKey specializes some of them for specific interfaces like SDCard, PWM, SPI and I2C buses, console UART, but most of them are left available for I/Os.

Button Interrupts

However, in order to detect when the buttons are pressed / released efficiently, the best solution is for them to generate an IRQ (Interrupt ReQuest) to warn the CPU that the corresponding button state has changed, instead of using an inefficient regular polling method.

Unfortunately in the V3s, only PB0 to PB9 and PG0 to PG5 support this GPIO IRQ capability. Worse, most of the pins PB0 to PB9 are already used for UART, I2C or PWM functions.

It is possible to route these functions to different pins and recover enough IRQ-capable GPIO pins: this is what we did for our #Funkey Zero project.

GPIO Expander

But for the FunKey device and given the small PCB size, this solution puts a lot of constraints on the PCB routing, at such a point that we decided to use a dedicated I2C GPIO expander chip to relieve the burden from the main V3s CPU.

A common chip for this purpose, that is well supported in the Linux kernel is NXP’s PCAL6416AHF.128. It is marketed as a “low-voltage translating 16-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers”: it just matches exactly what we need!

The connection with the V3s CPU is achieved using standard I2C clock (SCL) and data (SDA) signals, plus an additional IRQ signal driven by the I/O expander when pre-programmed conditions are met, such as a key press / release event. A RESET signal driven by the PMIC PWR_GOOD output is used to initialize the chip when required.


Here is the corresponding main schematic for the buttons:

The main component is of course the I/O expander U1, with the control signals to the CPU/PMIC on the east side.

The chip’s /INT signal is pulled up to the +3V3 power supply by the resistor R1, such that the active-low interrupt signal is disabled by default.

The I/O expander chip features 2 separate power supplies VDD and VDDP for the core and peripheral respectively, each decoupled by a bulk capacitor C1 and C2.

Except for the GPIO I/Os, the only remaining pin is the ADDR pin 18 which provides the I2C address LSB bit, so that you can address 2 PCAL6416AHF.128 chips on the same I2C bus by wiring this pin differently.

One oddity is that the pin 6 (P0_5) is connected to the /RESET signal: it is a routing trick to get this signal to go through this pin pad, as it was very difficult to access it otherwise…

The “Start” and “Select” buttons S1 and S2 are 2 low-profile SMT tactile switches, each featuring an ESD protection TVS diode D8 and D5, as these buttons are of course accessible by the user!

The other buttons are wired in the same fashion:

The “U”, “L”, “D”, “R”, “A”, “B”, “X” and “Y” buttons S3, S4, S5, S6, S8, S9, S10 and S11 are of the same kind and also have a respective TVS diodes D2, D3, D4, D5, D6, D7, D8, D9, D10 and D11.

The left (S12) and right (S7) shoulder buttons are right angle SMT tactile buttons, with their TVS diode D1 and D12.


The main advantage of this solutions is that the 12 signals to wire the buttons to the CPU are replaced by only 4 signals, from which 3 are shared with the other I2C peripherals (the PMIC) on the bus.

It is then much easier to route this dense PCB by delegating the button GPIO handling to a satellite chip.

Schematics: Console

The Allwinner V3s provides 3x UARTs (UnAsynchronous Receivers / Transmitters): UART0 with only RX and TX signals, and UART1 and UART2with additional RTS and CTS flow control signals.

As almost all SoCs, tha Allwinner V3s provides a serial console as a control terminal for debug or normal operation. By default, it is mapped to UART0, and it is used by the BROM (Boot Rom), the U-Boot bootloader and by the Linux kernel to output messages during the boot process, and later by the Linux kernel to log messages during normal operation. Depending on the configuration, it can be used too for loging into the system over an UART.

The Console schematic only requires a minimum of external components:

Besides the 3-pin 1.27 mm  (0.05″) pitch header J1 that will not be mounted on standard products, there is only a single series resistor R3.

What is the purpose of this resistor?

  • As explained previously for the SD Card clock signal, this may be to prevent ringing. But given the relatively slow signal speed (115200 bps), it is not the case here
  • If it were placed on the RX input signal, this could prevent frying the input pin if a large voltage (+5V, for example) is applied to it by dissipating the excessive voltage as heat in the resistor. It is not the case here, since the resistor is on the TX output signal, but we could have one added, if only we had some space left on the board…
  • In fact, the resistor is on the output TX signal to prevent short-circuits if the serial cable is reversed and the 2 TX outputs are connected together, one driving the signal low, while the other is driving it high: again in this case, the voltage difference between the 2 outputs will be burned as heat in the resistor, saving the output buffers!

Note that there is no ESD protection TVS diodes: this interface is not supposed to be mounted in the final user device, and PCB space is really constrained in this area, so they are omitted.