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Schematics: SPI LCD

SPI LCD Screen

One of FunKey’s strong point is certainly its screen: in a chosen form factor of roughly 45x45x15mm (1.75×1.75×0.6″), it has to be comfortable enough to provide a good gaming experience.

If in theory this allows to shoehorn a 2.4″ (diagonal) square screen, in practice, these screens are seldom square and more rectangular in shape.

Unless you are a large manufacturer and selling millions of devices, you are limited to using the screens that are available on the market, which most of the time were designed for a long-forgotten specific devices (think of PDAs, MP3 players, clam-shell phones, pods, etc.) and standard aspect ratio are either 5:3 or 16:10. Thus, for a given pixel technology, this results in rather standard screen sizes.

So the next size down is 1.8″, but these screens tend to be quite thick and based on an old technology, so their typical resolution is rather limited @ 128×160 pixels: too small for gamers.

Still going down in size, you can find 1.5~1.55″ screens with an interesting resolution of 240×240 or even 320 x 320 (“Retina”) pixels, but most of them use a fast and complex MIPI DSi interface requiring a dedicated controller on the host side. These screens were popular as the screen used in 6th-generation iPods, but unfortunately, getting a retail CPU with a MIPI DSi interface is almost impossible.

Fortunately, we found this 1.54″ LCD screen on AliBaba:

What makes this screen remarkable is its standard SPI interface, which like the MIPI DSi one, only requires a few wires and thus a narrow flex cable, easy to roll into a hinge.

This 1.54″ display has 240×240 16/18-bit full color pixels and is an IPS display, so the color looks great up to 80 degrees off-axis in any direction.

Be careful though, as in order to achieve a 30 fps @ 240 x 240 pixel resolution in RGB666 (3 bytes / pixel), this requires a ~40 MHz SPI clock rate. Once again, we were fortunate as both the V3s CPU and the screen built-in controller (a Sitronix ST7789V) support this high clock speed (after checking with the manufacturer and despite the controller datasheet specifies only a serial clock cycle (Write) of 66 ns or 15 MHz!).

We were even luckier as its backlight consists in 3 white LEDs in parallel and not in series, such that no additional step-up DC-DC converter is required, as a standard 3.3V / 60 mA (typical) power supply is sufficient. Of course, we won’t be able to drive this current directly from a CPU GPIO and the backlight will require an additional transistor to interface to the LCD backlight.

Its flex cable requires a mating Hirose 0.4 mm pitch DF37NB-24DS-0.4V dual row SMT connector, out of which only one single row is actually used.

Schematic

The schematic is thus quite simple:

The main component is of course the Hirose screen connector J3, with the following signals:

  • LEDA: the backlight LED Anode connection (+)
  • GND
  • +3V3 power supply
  • /SPI_CS: SPI Chip Select
  • SPI_MOSI: SPI Master Out / Slave In
  • SPI_CLK: SPI Clock
  • RS: LCD-specific Register/Memory Select (or Data/Control Select)
  • /RESET: LCD Reset

All data signals feature an ESD TVS protection diode D19-D20, and except for the power supplies and LEDA + /RESET signals, all signals are directly connected to the V3s CPU’s SPI interface, so there is not much to say about these.

The /RESET signal is currently tied to the PMIC PWR_OK output, but in a future revision, we plan to change this so it is instead controlled from a CPU GPIO pin.

Backlight PWM

The backlight control requires a few more components: a MOSFET-P transistor Q1 and 2 resistors R5 and R7 to provide its polarization, more on this below.

As the backlight LEDs cathode (-) pin are directly tied to GND within the screen, we need to drive these LEDs “from the high-side”, i.e. between the +3V3 power supply and the LEDA pin, so a MOSFET-P transistor is necessary:

As we want the backlight to be on by default, we need to drive it to GND by default: this is the role of R7. The role of R5 is then to make sure that -Vgs is driven below its threshold voltage and turns off the transistor when the CPU drives a GPIO high.

As an ultimate sophistication, we can drive the backlight from the CPU using one of its PWM built-in controllers with a varying duty-cycle, thus controlling the LCD backlight brightness accurately.

Schematics: DRAM Power

The attentive reader may have noticed that the PMIC covered in the previous log only provides 2 out of the 3 required DC-DC…

This is because the AXP20x is originally the PMU (Power Management Unit) used by most Allwinner SoCs (A10, A13 and A20), which do not integrate SDRAM, so the board designer has a wide choice of memory option: DDR2, DDR3, DDR3L, LPDDR3, LPDDR4 with various voltage requirements.

But no specific PMIC was created for the Allwinner V3s used in the FunKey device which however integrates a fixed SIP (System In Package) 512Mbit (64MB) DDR2 SDRAM.

We thus have to design a separate SMPS (DC-DC) power supply for providing the +1.8V 1A required for the DDR2 DRAM power supply.

For this purpose, we followed closely the Allwinner Reference Design which provides the same circuit, based on common pin-compatible SY8088 or LP3220 Chinese Buck DC-DC converter chips. But since these chips are not easy to provision in our place, we replaced it by a performance and pin-compatible AP3418KTR-G1 chip.

Here is the corresponding DRAM Power schematics:

Nothing very fancy here: the SMPS chip U4 has its required input filter capacitor C37 and output capacitors C65 and C73.

The low-profile ferrite-core power inductor L6  (rated with a saturation current of 1.76A and low < 0.1 ohm resistance) provides the DC-DC energy storage element.

The R20 / R23 precision voltage divider provides the required +0.6V feedback voltage from the +1.8V output voltage by having a 1/3 resistor ratio.

The last component is a pull-up resistor R19 which ties the SMPS chip enable input to its active level permanently. The pull-up voltage is +3.0V (just as in the original reference design), probably as it is the next higher voltage available, in order to limit the current in it to its lowest possible value.

OK, all power supplies are now covered!

Schematics: PMIC

From the previous logs, we can summarize the V3s power supply requirements to:

  • SMPS for +3.3V / 1.2A for the I/O power supply
  • LDO for +3.3V_AO / 30 mA for the Always-On power supply (RTC timer)
  • LDO for +3.0V / 200 mA for the analog power supply
  • SMPS for +1.8V / 1A for the DDR2 DRAM power supply
  • SMPS for +1.25V / 1.6 A for the core power supply

On the LicheePi Zero board used in our FunKey Zero prototype, a triple SMPS EA3036 is used for generating these +3.3V, +1.8V  and +1.2V voltages, with an additional XC6206 LDO for the +3.0V (the +3.3V Always On is connected directly to +3.3V). Although compact (the EA3036 is a tiny 3 mm x 3 mm QFN20 package), this solution is not ideal as it does not provide a battery charger and monitoring capability, which is a requirement for the FunKey device.

PMICs

Sophisticated SoC requiring multiple voltages, high current and proper sequencing are common today and hopefully, all major manufacturers generally provide dedicated companion chips called PMICs (Power Management Integrated Circuits), in charge of these tasks. Allwinner is not an exception through its sister company X-Powers.

Their AXP20x products are highly-integrated PMICs that are optimized for applications requiring single-cell Li-battery (Li- Ion/Polymer) and multiple output DC-DC converters.and LDOs. Here is a block diagram:

The AXP20x features:

  • A wide choice of input power source, the best source is chosen as IPSOUT inside the IPS (Intelligent Power Select) block :
    • USB VBUS
    • Battery BAT
    • ACIN wall plug (not used in FunKey)
    • BACKUP battery (not used in FunKey)
  • A 1.8A fast PWM battery charger (also called DC/DC1) with battery voltage / current sense and programmable charge indication LED
  • A soft key power-on/off logic with timer (just as in smartphones!)
  • An I2C interface with interrupt signal to communicate with the CPU
  • An optional battery temperature monitoring if the battery is equipped with an NTC resistor (not used in FunKey)
  • A reference voltage
  • A built-in 12-channel 12 bit ADC that measures various voltage and current data, as well as feeding an internal Coulomb counter and fuel gauge system (more on this later)
  • A power OK output used to generate the global RESET signal in FunKey
  • 5x GPIOs (not used in FunKey), GPIO0 can be programmed as LDO5 output
  • 2x DC/DC SMPS DC-DC2 and DC-DC3
  • 5x LDOs (only 2 are used in FunKey, LDO5 is optionnaly output to GPIO0)

Looking at their datasheets, it is difficult to tell the difference between the AXP202AXP203 and AXP209 (any hint welcome!). In the FunKey design, we use an AXP209 because it is the one that comes along with the V3s when you buy it on AliExpress 😉

AXP20x Application Diagram

For complex dedicated chips like this, the best option is to follow as much as possible the application diagram and reference design given by the manufacturer, as the internals of the chips are seldom fully disclosed, so you need to take their word on some of the external component values to use.

The Allwinner V3s Reference Design contains on page 6 the schematics for using an AXP203 to supply the power to a V3s-based dashboard camera design. It follows closely the reference designs provided in the AXP20x datasheets:

More hints are provided in my self-translated V3s Hardware Design Guide (page 7) too.

FunKey PMIC Design Adaptation

The FunKey device uses all AXP209 integrated SMPS:

  •  the PWM charger DC-DC1
  • the DC-DC2 for providing the +1.25 V / 1.6A for the core
  • the DC-DC3 for providing the +3.3V / 1.2A for I/Os

But compared to the sophisticated reference designs, the FunKey device only uses 2 out of the 5 integrated LDOs:

  • LDO1 supplies the +3.3V / 30 mA Always On for the RTC
  • LDO2 provides the +3.0V / 200 mA for the analog power supply
  • LDO3 / LDO4 / LDO5 are not used by FunKey

Here is the Funkey schematic block for the PMIC:

This schematic may look intimidating and complex, but it is in fact just a collection of simple basic elements, and it is actually very close to the manufacturer-recommended design.

The most noticeable difference is that the FunKey schematics use symbols and placement that are as close as possible to their corresponding physical package and layout, instead of defining symbols that are conveniently arranged by logical properties. Even if this makes schematics more complex at first sight, the benefit of this approach is that the step to go from the schematics to the physical layout become much easier, and so is the debugging of the physical board, which is then very close to the schematics too.

Another habit that is used everywhere in the FunKey schematics is that all signals (except power supplies and GND) are routed using explicit wires, rather than counting on invisible connection by net names and relying of the reader to search these names all over the place. This forces related components to be clustered in compact groups to shorten the wires, and put more focus on inter-cluster signals, with a natural inclination to unravel wire nests in the schematics before laying out the actual board.

And there are some  “PWR_FLAG” symbols added here and there, which is the proper way in KiCAD to declare that a given net has a proper supply and thus prevent the ERC (Electrical Rule Check) to throw an error.

The end of this log details each PMIC function one by one:

Power Inputs (East side)

A wall-plug AC adapter input is not used in the FunKey device, so +VIN is just filtered using C75 on pins 32 and 33.

The USB power input +VUSB on pin 31 is filtered using C70, and the best (between +VUSB and +VBAT) available voltage is output to +VOUT on pins 34 and 35 and filtered using C78.

The BACKUP supply on pin 30 is not used and is left unconnected.

Internal Connections (All sides)

Some AXP20x signals are externally available and should be connected to external components:

  • The +2.5V internal logic voltage VINT on pin 26  is filtered using the recommended value for C67
  • The reference voltage VREF on pin 24 is decoupled with C64, and its BIAS connection on pin 23 is connected to a precision 200k 1% resistor R22, as recommended

Additionally, the AXP20x is actually made up of separate flexible blocks that require external interconnections to set their desired operation:

  • All DC/DC inputs (VIN1 on pin 44, VIN2 on pin 7 and VIN3 on pin 14), as well as LDO3IN input on pin 40 are connected to the best available voltage +VOUT with filter capacitors C59, C23, C30, and C69, respectively
  • LDO1SET on pin 27 is used to set the initial voltage of LDO1, and according to the datasheets, setting it to VINT sets its voltage to the desired +3.3V for the +3.3V Always On power supply
  • OTOH, combined LDO 2 and 4 input LDOIN24 on pin 13 is instead connected to +3.3V in order to minimize the voltage drop for LDO2 to generate the +3.0V. Here too, there is a filter capacitor C34
  • It is not clear what is the exact function of APS on pin 21 (it is described as “Internal Power Input”), but it is to be connected to +VOUT, too

DC-DC1 PWM Battery Charger (North East side)

The battery is connected to J5 (a 2-pin JST 1.0 mm pitch receptacle) and uses R21 as a precision current sense resistor, with C53/C56/C60 filter capacitors and L5 (a low-profile ferrite-core power inductor rated with a saturation current of 1.2A and low < 0.1 ohm resistance).

Please note that the battery is not protected on the board against reversing polarity, as the model used already contains a built-in protection.

R24 is mounted to simulate a battery NTC for measuring temperature, as the chosen LiPo battery does not feature this temperature sensor.

A user-programmable (through the I2C interface) charge LED D30 is provided, with its current-limiting resistor R26 (for which we need to raise the value as the LED is too bright!), as well as an TVS diode to prevent ESD, as the LED body will be accessible to to user.

DC-DC2 +1.25V / 1.6A (West side)

This SMPS is built around the ferrite core power inductor L3 and filter capacitors C26 and C29.

DC-DC3 +3.3V / 1.2A (South side)

This SMPS is built around the ferrite core power inductor L4 and filter capacitors C39 and C43.

LDO1 +3.3V Always On 30mA (South East side)

The LDO output on pin 28 is filtered with capacitor C72.

LDO2 +3.0V / 200mA (South West side)

The LDO output on pin 12 is filtered with capacitor C38.

LDO3 (North side)

This LDO is not used and its output on pin 41 is nevertheless filtered with a capacitor C63.

LDO4 (South West side)

This LDO is not used and its output on pin 11 is nevertheless filtered with a capacitor C38.

Power Key (North West side)

The AXP20x features a soft power key with internal short and long-press detection with user-programmable time settings, which enables turning power ON or OFF much like the way it is done in cellular phones.

Only a few external components are required: the tactile switch S13, its ESD protection TVS D29, and a low-pass filter R18 and C42 for debouncing the switch.

I2C Bus (North West side)

The AXP20x can be externally controlled by the main CPU using the I2C bus on pins 1 and 2. This bus has pull-up resistors to +3.3V R14 and R16, and the IRQ/WAKEUP signal on pin 48 enables warning or waking up the CPU on a selection of AXP20x-generated events, with a pull-up resistor R13 to +3.3V..

GPIOs (South and West sides)

GPIO0-3 on pins 19, 18, 5 and 3 are not used and are left unconnected.

PWROK (South West side)

The PWROK signal on pin 25 is used to generate the global RESET signal for the whole board, with a pull-up resistor R15 to the +3.3V Always On power supply.

Enable Signals (West side)

The global chip enable signal N_OE on pin 4 is always activated through a 2k resistor R17 to to GND.

The USB enable signal N_VBUSEN on pin 6 is directly tied to GND to always enable power from the USB bus.

Monitoring

Through the I2C bus and the numerous internal available registers, the AXP20x provides a very good control of its operation, including many threshold and timing settings, but also many voltage and curent monitoring values.

Coulomb Counters / Fuel Gauge

 It is well known that battery discharge voltage curve over time is very flat, making it very difficult to estimate the real charge/discharge state of the battery. Moreover, these states will vary with temperature, load, and aging.

The only accurate way to monitor the battery status is to actually count the energy that is stored when charging, and the one that is consumed. This particularly important feature is achieved in the AXP20x using a dual Coulomb counter which continuously sums the current intensity over time for monitoring the battery accurate charge and discharge status, with user-defined alert thresholds.

This fuel gauge is providing the ability to precisely report the remaining battery capacity, just like people are used to with cellular phones.

Why so many different Power Supply Voltages?

Looking back at the previous log on the CPU schematics, the FunKey device clearly needs a sophisticated power supply in order to fulfill the CPU power requirements. They are recalled below, along with the maximum current requirements found in the Allwinner V3s reference design (page 3):

  • +3.3V / 1.2A for the I/O power supply
  • +3.3V_AO / 30 mA for the Always-On power supply (RTC timer)
  • +3.0V / 200 mA for the analog power supply
  • +1.8V / 1A for the DDR2 DRAM power supply
  • +1.25V / 1.6 A for the core power supply

But why in the first place are so many different power supply voltages required?

Power Efficiency

A first answer is: for better power efficiency.

As P = U x I (Electrical power is the product of voltage level by current intensity), you can reduce power by decreasing the required current or reducing the operating voltage. Assuming you already do your best to reduce the required current, you can still reduce power by reducing voltage.

Reducing Power Supply Voltage

Voltage Drop

But how far can you go? Over long distance, you have the voltage drop from the conductor linear resistance, but this effect can be neglected for small boards. 

Noise Margin

You have inductive and capacitive coupling between conductive wires and planes too, but within a PCB, these coupling only have a limited direct effect on voltage. However, these coupling play a role in that they will pick up external electromagnetic noise from the surroundings and inject it into the circuit.

And with digital circuits, a critical limit when lowering the operating voltage is the “noise margin” or difference in absolute voltage levels between a logical ‘0’  and logical ‘1’, which determines the maximum amplitude of spurious voltage spikes that a conductor can pick up that will trigger an erroneous logic level change.

This phenomenon mostly depends on the circuit scale: a long-distance circuit between boards will require higher voltages (typically +12V or +24V) to limit this effect, whereas a circuit between boards a few meters apart or using through-hole chips on the same board wile require a lower voltage (typically +5V like the old Arduinos). Using SMT chips will allow even smaller boards and lower voltages (+3.3V is today typical), and with wires running on the same silicon die, it is possible to go down to +1.2V, given the current technological limits.

Voltage Swing

There are other reasons why you should try to minimize voltages: the core CPU for example needs to run as fast as possible, and lowering its operating voltage will shorten the signal rise and fall duration as the voltage swing is reduced.

Other Power Supply Considerations

Besides reducing the operating voltage, there are other considerations that may push to multiply the number of power supplies in a design:

Quiescent Current

As for power supply used for standby operation providing small currents,  a very-low leakage current (“quiescent current”) is required as it can no longer be neglected compared to the current required by the light load and even more importantly because this current consumption is permanent.

Ripple Voltage

For sensitive circuits such as ADCs (Analog to Digital Converters) or PLLs (Phase-Locked Loops) which rely on comparing very small voltage differences, a “clean” power supply featuring very low ripple voltage amplitude is required to achieve a good resolution and/or accuracy. This characteristic is only possible to obtain using LDOs and not SMPS, and the figure to pay attention to is then the PSRR (Power Supply Rejection Ratio) or how much a variation in the input voltage will affect the output voltage: the higher, the better! A value > 50 dB is a good starting point.

Application to the FunKey Design

Based on these considerations, it is now clear that each V3s power supply voltage has a good reason to exist:

  • +3.3V / 1.2A is used for powering the I/Os to connect between chips on the board. Given the required current, a SMPS is required for reaching a good efficiency
  • +3.3V_AO / 30 mA for the Always-On power supply (RTC timer) requires a low quiescent-current, so an LDO is used
  • +3.0V / 200 mA for the analog power supply also requires an LDO, this time to minimize the ripple voltage
  • +1.8V / 1A for the DDR2 DRAM power supply: this strange voltage level is typical for DDR2 DRAM memory chips, and is the result of driving the large memory array inside the chip
  • +1.25V / 1.6 A for powering the CPU core to minimize the voltage swing and increase the possible CPU frequency. Given the required current, a SMPS is required for reaching a good efficiency, too

Regulated DC Power Supply Topologies

Simple DC electronic circuits can be powered by directly connecting a battery.

However, circuits usually require a constant input voltage for proper operation.

This log is a small parenthesis to explain the different regulated DC power supply topologies, before looking at the FunKey power supply schematics in details.

If you are already comfortable with this subject, you can skip this log entirely!

Linear Regulators

The easiest method to achieve this constant load voltage despite a varying source voltage is to linearly control the resistance of the regulator in accordance with the load, resulting in a constant output voltage.

Shunt Regulator

The simplest voltage regulator is the shunt regulator, built around a Zener diode which most interesting characteristic is to maintain a constant voltage across itself when the current through it is sufficient to take it into the Zener breakdown region. A simple shunt regulator looks like this:

Series Regulator

By adding a emitter-follower transistor to the simple shunt regulator, the small base current of the transistor forms a very light load on the Zener, thereby minimizing variation in Zener voltage due to variation in the load, resulting in a better regulation. Here is a schematic for this series regulator:

Integrated Linear Regulator

In integrated voltage regulators, the discrete Zener diode is replaced by a more sophisticated (but easier to integrate) circuit built around a resistor divider feeding an operational amplifier, a voltage reference, and a transistor driving the emitter-follower pass transistor:

Usually, the pass transistor and its driving transistor are combined into a single Darlington transistor plus a controllable current source like this:

LDO (Low Drop-Out) Regulator

The above circuit works well, but its drop-out voltage (the difference between the input and output voltage) is rather high because of this transistor cascade, around 1.5V to 2.5V.

By replacing the emitter-follower Darlington transistor by a PNP transistor in an open collector or open drain topology, the drop-out voltage is reduced to 0.7V or lower:

SMPS (Switched-Mode Power Supply) or DC/DC Converters

A linear regulator provides the desired output voltage by dissipating excess power as heat in the Zener diode or in the pass transistor. Hence its maximum power efficiency is VOUT/ VIN since the volt difference is wasted to heat the birds.

In contrast, a Switched-Mode Power Supply changes output voltage and current by switching non-linear storage elements, such as inductors, transformers and capacitors between different electrical configurations.

These elements are non-linear because the inductor and transformer respond to changes in current by inducing its own voltage to counter the change in current, whereas a capacitor responds to changes in voltage by inducing its own current to counter the change in voltage.

Thus, depending on the way the components are arranged, it is possible to obtain SMPS circuits that either have an output voltage higher than the input voltage (“Boost Converters”), or lower than the input voltage (“Buck Converters”, as is it subtracts or “Bucks” the supply voltage).

Because of technology, power inductors are easier to manufacture, take less space and are more stable over time than their counterpart capacitors. This is why most power DC/DC converters are built using inductors. Capacitor-based SMPS are generally used for lower power applications, such as for generating the +12V and -12V voltages required by true RS232 from a +3.3V or +5V power supply in the ubiquitous MAX232 drivers.

Boost Converter

The most basic circuit for the Boost converter is the following:

If the switch is driven by a square wave, the peak-to-peak voltage of the waveform measured across the switch can exceed the input voltage from the DC source. This is because the non-linear characteristic of the inductor, and this voltage adds to the source voltage while the switch is open.

Please note that in this converter, the output voltage is not isolated from the input voltage.

Buck Converter

The corresponding basic circuit for the Buck converter is the following:

The way this converter works is described in details here. Basically, when the switch is closed, the inductor will produce an opposing voltage across its terminals in response to the changing current, reducing the output voltage, and meanwhile the inductor stores this energy in the form of a magnetic field. When the switch is opened,  the current will decrease and will produce a voltage drop across the inductor, and now the inductor becomes a current source, where the stored energy in the inductor’s magnetic field is restored and fed to the load.

Please note that in this converter too, the output voltage is not isolated from the input voltage.

Isolated SMPS

Isolated Switched-Mode Power Supplies use a transformer to isolate the input voltage from the output voltage, and thus can produce an output of higher or lower voltage than the input by adjusting the turns ratio.

Advantages and Disadvantages

Linear regulators are simpler than SMPS, and their linear behavior produce a very clean output voltage, but their efficiency is directly proportional to the difference between the input and output voltage, which is dissipated as heat.

However, for light loads and/or when the voltage drop-out is low, LDOs are very useful.

OTOH, SMPS are more complex and require more components, but their efficiency is much better (typically 80-90%), resulting in less heat, with the drawback of a switching electrical noise pollution of both the input voltage (that may couple electrical switching noise back onto the mains power line) and the output voltage (with electromagnetic interference (EMI) and a ripple voltage at the switching frequency and all its harmonic frequencies).

SMPS are thus almost exclusively used when heavy loads are used and/or when the voltage drop-out is important.

Schematics: CPU

Schematics: CPU

At the heart of the FunKey electronic design is the CPU block, built around the Allwinner V3s chip:

We selected this particular chip because it features a built-in 64MB DDR2 DRAM, which is very good as it saves some precious real-estate on the PCB and also because its layout is much easier: usually because of the mandatory high-speed signals, DDR DRAM requires both length and impedance-matching on all critical signals, leading to the weird “snake”-style layout to balance traces. As here the DDR DRAM is bonded to the CPU into the same package, there is no such requirement here.

OTOH, 64 MB DRAM may not seem much, but we determined that it is sufficient for our modest retro-gaming needs.

One bonus with the V3s is that it comes into a non-BGA (Ball Grid Array) LQFP128 package with actual leads, which is much more user-friendly for prototyping!

Here is the part of the schematics corresponding to the CPU core:

SoC Blocks

As one can see, there is not much besides the CPU chip U3 itself… But it can also bee seen that the CPU is in fact a SoC (System on Chip) containing a collection of built-in peripheral and memory blocks along with the CPU itself:

  • the LCD / CSI display peripheral
  • the GPIO port G / SDC1 (SD Card #1) interface
  • the AUDIO codec
  • the LRADC0 (Low-Resolution Analog to Digital Converter)
  • the USB OTG controller
  • the GPIO port F / SDC0 (SD Card #0) / UART0 interface
  • the RTC (Real Time Clock) timer
  • the EPHY (Ethernet PHYsical) interface
  • the MIPI camera interface
  • the built-in 64 MB DDR2 DRAM
  • the GPIO port C / SPI interface
  • the GPIO port B / UART2 / PWM0 / PWM1 / TWI0 (I2C #0)  / TWI1 (I2C #1)

Among these, the FunKey device only uses a few blocks: the AUDIO, USB (as device only), SDC0 (for SD Card), RTC, DRAM, SPI (for the LCD screen), PWM0 (for backlight), TWI0 (for I2C bus to control the GPIO expander and power management chips) and a couple of GPIOs to power the audio power amplifier and get feedback interrupt signals from the the GPIO expander and power management chips.

CPU Power Supplies

What is remarkable though is that the V3s requires a lot of different voltages for its power supply:

  • +3V3 for the I/O power supply
  • +3V3_AO for the Always-On power supply (RTC timer)
  • +3V0 for analog power supply
  • +1V8 for the DDR2 DRAM power supply
  • +1V25 for the core power supply

This profusion of different power supplies as well as the high power drawn by some of them (1.2A for +3V3, 1.6A for +1.25V) requires a sophisticated power management that will be detailed in a future log.

LRADC0

The LRADC0 (Low-Resolution Analog to Digital Converter #0) is designed to measure the voltage of a resistor ladder switched by keyboard keys: this single input is thus in theory able to manage a keyboard of up to 10 keys @ 250 Hz.

Unfortunately, the FunKey has 12 keys (U/D/L/R, A/B/X/Y, RR/RL, START and SELECT), and the resulting key detection accuracy is not compatible with a gaming usage because of long term stability problems. This is the reason why it is not used in the FunKey and just terminated by a proper low-pass filter R6/C9 to avoid picking up noise glitches.

SD Card

The SD Card interface is almost a direct connection between the chip and the dedicated SD Card connector. Only a single series resistor R8 is required on the clock line in order to prevent ringing.

Crystals

The V3s chips requires 2 crystals: one low-frequency 32.768 kHz crystal Y1 for the RTC clock and one high-frequency 24 MHz crystal Y2 for deriving the 1.2 GHz clock.

The 24 MHz crystal is used by an internal oscillator to lock the phase of the 1.2 GHz oscillator using a PLL (Phase-Locked Loop).

The 32.768 kHz crystal is used by another internal oscillator to tick the RTC (Real-Time Clock) at a standard watch frequency.

These crystals require 2 load capacitors (C12/C13 and C14/C15) each in order to guarantee that the oscillators still start and work with a comfortable operation margin taking into account voltage, temperature and aging.

The 32.768 kHz crystal features an additional high-value resistor R12 in order to limit the internal oscillator’s output current and thus reduce further the RTC timer power consumption.

For more details on crystal oscillator design, please check this application note from STM.

DRAM

The DRAM within the V3s chip is a DDR2 one, meaning that its data lines are clocked using both edges of a 400 MHz clock signal.

At these high frequencies, even short wires have a length that is of the same order of magnitude as the signal’s wavelength and thus each signal should be considered as a transmission line, for which impedance must be matched to avoid signal reflections, requiring termination resistors on the data lines DQx.

DDR2 or DDR3 DRAMs feature merged drivers and dynamic on-chip termination like this (“VDDQ/2” is labeled “SVREF” in our schematic):

The V3s DDR2 DRAM has an active termination calibration circuitry and procedure called “ZQ Calibration” requiring an accurate 1% 240R resistor R11 (and NOT 240K like shown in the schematic, my mistake!) connected internally like this:

More on the DDR2 DRAM ZQ Calibration subject can be found in this Micron Application Note.

This concludes the study of the FunKey CPU core schematic block.

Electronic Parts

The main part in the FunKey device is of course the CPU: an AllWinner V3s SoC with integrated 64MB DDR2 DRAM. Not much compared to a Raspberry Pi for example, but it turns out it has just the right capacity for our purpose, and a minimum size because of its integrated DDR2 RAM, without the length and impedance-controlled constraints on PCB trace requirements.

The V3s also features a low power consumption and all the required peripheral that we need.

The V3s CPU is generally used with a companion AXP209 PMIC chip in charge of supplying all the required voltages for the CPU: +3V3, +3V3 (RTC), +3V0, +1V25, most of these using integrated DC/DC buck converters or simpler LDOs for the ones requiring the less power. The AXP209 also features an integrated Coulomb counter for monitoring the available battery power, as well as a soft-power switch controller that acts just like the one in your smartphone!

A separate AP3418KTR-G1 DC/DC converter is sued for providing the DDR2 DRAM +1V8 power.

The second most important part in our design is probably our small 1.5″ LCD screen. It has an amazing 240 x 240 pixel resolution, while using a simple SPI-based interface and not a complex DSi interface based on the differential high-speed MIPI specification, which requires a dedicated controller that is only available in higher-end SoC:

For audio playback, we wanted to have an internal speaker. But given the reduced dimensions, we tried to find the smallest available one, which has a very small 10 mm diameter, with a total height of 2.9 mm, out of which 1.4 mm can be inserted into a PCB hole, thus only having a height above PCB of 1.5 mm:

We use a simple mono audio playback through a PAM8301AAF amplifier. This amp has all the required characteristics, with a filterless (no capacitor) design.

After testing tactile domes in our FunKey Zero prototype, we decided to go back to standard tactile switches, as their placement can be done by a regular SMT pick&place machine with a very good accuracy, just like all the other components on the PCB, unlike the tactile domes which require an adhesive tape to place them, making them less accurate in their absolute positioning.

We also need some right-angled tactile switches for the rear left and right buttons:

We took the smallest we could get, but we may experiment with softer (no-click) ones for the rear buttons to bring a better play experience.

For the microUSB connector we choose a common mid-mount model with through-hole pins in order to avoid tearing it off the board if you don’t pull the chord straight. 

The only remaining mechanical part is the small DF37NB-24DS-0.4V(51) connector, matching the LCD screen connector.

For debug, we features a 3-pin  1.27 mm pitch header, with console UART RX, TX and GND pins.

The only remaining active part is a P-MOSFET used to drive the screen backlight from a V3s GPIO pin.

We use TVS diodes on all user-accessible parts to prevent ESD (these are small 0402 TVS), and a dedicated USB ESD protection a close as possible to the USB connector.

All other parts are passive resistors, capacitors or ferrite beads in 0402 form factor whenever possible, as we don’t have a lot of available real estate on this board.

As you can see, none of the components was chosen randomly, and finding the right part took us a significant amount of time!

Schematics: USB

In the FunKey device, the USB interface has 2 purposes:

  • provide an external power supply source for both powering the device and charging the built-in LiPo battery
  • provide a data interface to transfer firmware upgrades, configuration files, game emulators and game ROMs

The first purpose only requires the +5V USB power and GND pins. The second purpose requires to wire the additional differential data lines D+ and D-. As we only need to operate as an USB device and although the V3s is able to work as either an USB host or USB device using the USB OTG protocol, we don’t need the ID pin to determine by the cable wiring which role we must take.

The USB schematic is the following:

Before connecting 2 devices using an USB cable, they may be at completely different absolute voltages, and during cable insertion, the shield will be in contact before the other pins, including GND. The C6 capacitor between the Protective Earth (Shield) and GND is here to provide an AC path for sinking this difference in voltage and align the GND levels when plugin the cable. 

The resistor R4 on the USB ID connector pin should probably not be mounted: as we act only as an USB device, this pin should be left floating.

The capacitors C7, C8, C10 and ferrite bead L2 form a constant-k 3 pole CLC low pass filter to remove any spurious in/out on the USB power supply wire. The USB 2.0 specification limits the maximum bulk capacitance value to 10 µF in order to avoid power supply excessive droops when plugin in a device with a discharged large bulk capacitor.

D15 is a combined TVS protection diode for the VBUS pin and a set of clamping diodes that will limit the voltage on D+ and D- pins to stay between GND and VBUS levels to  in order to protect the V3s USB driver from under / over-voltages.

Schematics: Audio

Playing audio is absolutely part of the gaming experience!

So for a retro gaming console like the FunKey, we need to have a decent audio playback, despite its lilliputian size.

By decency, we discarded the solution using a piezo-electric buzzer: these can get a loud sound in a small volume, but only at their resonance frequency, so the sound quality is extremely poor.

Turning back to the solutions used in modern smartphones as an example, there are 2 paths to consider:

  • playing audio internally by the mean of speaker(s)
  • playing audio externally by using headphones, with or without a cord

The speakers used in today’s smartphones are rather sophisticated and achieve very good performance. However, these are using made-to-measure speakers and cavities, such that they cannot be found and reused as standard parts in a design like ours.

As for the external audio solution, we have a problem: the FunKey is so small that it is not possible to integrate an audio jack to connect headphones! And despite our search, there is no simple and small enough way to use Bluetooth to output audio to cordless headphones either.

The best solution we have found consists in using a single tiny speaker from CUI CDM-10008, that is able to output 72 dB spl @ 1m from a 0.3W input power, with relatively modest dimensions: 10 mm diameter and only a 2.9 mm thickness.

Connections are not easy though, since this speaker is meant to have wires soldered to its pads, but we are trying to convert it into an SMT device in order to gain space in our small enclosure! We don’t have a satisfying solution yet that is possible to use for mass production, we are still working on it!

Schematic

The resulting schematic is simple, as the Allwinner V3s already contains an analog stereo audio codec (coder/decoder): we only have to take one of its headphone output channel (left or right) and feed it to a mono audio amplifier.

We chose the PAM8301 chip because of its cheap price, good availability, its more than sufficient output power of 1.5W and its filterless operation, meaning that no bulky series capacitor is required to drive the speaker.

Here is the corresponding schematic:

We chose the right headphone channel HPOUTR that is fed to the audio amplifier U2 through a DC-bias filter capacitor C3.

The audio amplifier /SD shutdown input is driven by one V3s GPIO, with a pull-down resistor R2 to disable the amplifier by default.

The audio amplifier power supply is filtered using a ferrite bead L1 in order to eliminate high-frequency digital noise, and decoupled by 2 capacitors C4 and C5, as recommended in the device datasheet.

The speaker SP1 is driven in differential mode in order to get the maximum voltage swing and thus the maximum power available for a given output current.

Two ESD protection TVS diodes D13 and D14 are added, since the speaker may be accessible to the user through the enclosure grid in front of the speaker.

Schematics: Buttons

As a generic game console emulating many classic ones, the FunKey requires numerous buttons:

  • A soft “ON/OFF” button
  • A “+” control pad with “Up”, “Down”, “Left” and “Right” buttons
  • A “x” control pad with “A”, “B”, “X” and “Y” buttons
  •  “Start” and a “Select” buttons
  • L and R shoulder buttons

As we have sen in the log on the PMIC, the soft “ON/OFF” button is directly connected to the power management chip, so we are left with 4 + 4 + 2 = 12 buttons for game control.

GPIO Requirements

The Allwinner v3s CPU comes in a large 128-pin TQFP package, with a lot of exposed (51!) GPIO pins:

  • PB0 to PB9 (10)
  • PC0 to PC3 (4)
  • PE0 to PE24 (25)
  • PF0 to PF5 (6)
  • PG0 to PG5 (6)

The FunKey specializes some of them for specific interfaces like SDCard, PWM, SPI and I2C buses, console UART, but most of them are left available for I/Os.

Button Interrupts

However, in order to detect when the buttons are pressed / released efficiently, the best solution is for them to generate an IRQ (Interrupt ReQuest) to warn the CPU that the corresponding button state has changed, instead of using an inefficient regular polling method.

Unfortunately in the V3s, only PB0 to PB9 and PG0 to PG5 support this GPIO IRQ capability. Worse, most of the pins PB0 to PB9 are already used for UART, I2C or PWM functions.

It is possible to route these functions to different pins and recover enough IRQ-capable GPIO pins: this is what we did for our #Funkey Zero project.

GPIO Expander

But for the FunKey device and given the small PCB size, this solution puts a lot of constraints on the PCB routing, at such a point that we decided to use a dedicated I2C GPIO expander chip to relieve the burden from the main V3s CPU.

A common chip for this purpose, that is well supported in the Linux kernel is NXP’s PCAL6416AHF.128. It is marketed as a “low-voltage translating 16-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers”: it just matches exactly what we need!

The connection with the V3s CPU is achieved using standard I2C clock (SCL) and data (SDA) signals, plus an additional IRQ signal driven by the I/O expander when pre-programmed conditions are met, such as a key press / release event. A RESET signal driven by the PMIC PWR_GOOD output is used to initialize the chip when required.

Schematics

Here is the corresponding main schematic for the buttons:

The main component is of course the I/O expander U1, with the control signals to the CPU/PMIC on the east side.

The chip’s /INT signal is pulled up to the +3V3 power supply by the resistor R1, such that the active-low interrupt signal is disabled by default.

The I/O expander chip features 2 separate power supplies VDD and VDDP for the core and peripheral respectively, each decoupled by a bulk capacitor C1 and C2.

Except for the GPIO I/Os, the only remaining pin is the ADDR pin 18 which provides the I2C address LSB bit, so that you can address 2 PCAL6416AHF.128 chips on the same I2C bus by wiring this pin differently.

One oddity is that the pin 6 (P0_5) is connected to the /RESET signal: it is a routing trick to get this signal to go through this pin pad, as it was very difficult to access it otherwise…

The “Start” and “Select” buttons S1 and S2 are 2 low-profile SMT tactile switches, each featuring an ESD protection TVS diode D8 and D5, as these buttons are of course accessible by the user!

The other buttons are wired in the same fashion:

The “U”, “L”, “D”, “R”, “A”, “B”, “X” and “Y” buttons S3, S4, S5, S6, S8, S9, S10 and S11 are of the same kind and also have a respective TVS diodes D2, D3, D4, D5, D6, D7, D8, D9, D10 and D11.

The left (S12) and right (S7) shoulder buttons are right angle SMT tactile buttons, with their TVS diode D1 and D12.

Benefit

The main advantage of this solutions is that the 12 signals to wire the buttons to the CPU are replaced by only 4 signals, from which 3 are shared with the other I2C peripherals (the PMIC) on the bus.

It is then much easier to route this dense PCB by delegating the button GPIO handling to a satellite chip.